'How to see the synthesized RTL in openlane?

I have just started learning openlane. I want to see the RTL synthesis using openlane similar to how we get in vivado RTL synthesis. I have gone through the documentation but could not find anything regarding the same.

yosys


Solution 1:[1]

You can use write_verilog Yosys command after every step. E.g., do opt; fsm; opt and after those passes you'll have a refined RTL.

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Solution Source
Solution 1 SK-logic

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