How to control enable in your design in vivado?

Question

I am having two IPs in vivado one is pseudo randomizer and the another one is crc- 32(cyclic redundancy check ) the output of pseudo randomizer is connected to the input or crc as you can see in the image .

If I am sending 256 bits from the randomizer as message bits the 256 bits come out as the output of crc as message bits after the 256 message bits passes, my 32 crc bits are coming out. And when my these 32 crc bits are coming out I want that my randomizer input data stops flowing till the 32 crc bits passes so that there will be no data loss at next frame.

How can I control these message bits or where should I connect my enable of crc IP. Any suggestion is highly appreciated.

enter image description here

Answer 1

You will need to write an arbitration state machine to control the two blocks and handles the sequencing of which block runs at what time. The blocks should be written with an "enable" or "start" input signal and a "finished" or "done" output signal which provides the handshaking with the state machine.

This page has good explanations of how state machines (aka Finite State Machines) are normally constructed, their intent, and use cases.

An example state would be similar to the following and it would need to be in a clocked process:

case(arbiter_fsm)
  IDLE : begin
    // Don't do anything when there is no incoming data.
    randomizer_enable <= 1'b0;
    crc32_enable <= 1'b0;
    // If data is coming in, start randomizing.
    if(incoming_data == 1'b1) begin
      randomizer_enable <= 1'b1;
      arbiter_fsm <= RANDOMIZER;
    end
  end
  RANDOMIZER : begin
    randomizer_enable <= 1'b1;
    // Randomize until the data is finished coming in.
    if(randomizer_done == 1'b1) begin
      arbiter_fsm <= CRC32;
      randomizer_enable <= 1'b0;
    end
  end
  CRC32 : begin
    crc32_enable <= 1'b1;
    // Calculate the CRC until it is finished.
    if(crc32_done == 1'b1) begin
      arbiter_fsm <= IDLE;
      crc32_enable <= 1'b0;
    end
  end
  default : begin
    randomizer_enable <= 1'b0;
    crc32_enable <= 1'b0;
    arbiter_fsm <= IDLE;
  end
endcase