How to check in SystemVerilog that signal went high during simulation using ModelSim

Question

I need to check, whether during the testbenching the particular signal went at least for a single clock cycle to logic 1.

I've tested following asserts, which shall be equivalent:

    initial assert property (
        @(posedge clk_tree_x.ClkRsBST_ix.clk)
            s_eventually TS.TSUpdated) else
      $error("Was not active");

and

   initial begin
      assert property (@(posedge clk_tree_x.ClkRsBST_ix.clk)
               strong(##[*] TS.TSUpdated)) else
    $error("Was not active");
   end

In simulation using Mentor ModelSim SE64 2021.1 the results are extremely weird.

On first simulation pass the simulation completely ignores this assert. On second simulation pass ModelSim apparently uses results of previous simulation to announce before even the newly run simulation happens that the assert triggered:

#    Time: 2005087500 ps Started: 5 ns  Scope: tb_bst_provider.DUT.fook File: bst_provider.sv Line: 669
# ** Warning: (vsim-8777) Breakpointing based on severity while evaluating concurrent assertion is not supported.
#    Time: 2005087500 ps  Iteration: 0  Region: /tb_bst_provider/DUT File: bst_provider.sv

Not sure whether this is consistent behaviour to all strong properties, but it is hardly useful for any sort of unit testing, as the tests never run twice using the same parameters.

Is there any way how to assert that 'signal is not present through the simulation run', which actually works with modelsim?