How prompt is x86 at setting the page dirty bit?

Question

From a software point of view, what is the latency between an instruction that dirties a memory page and when the core actually marks the page dirty in the Page Table Entry (PTE)?

In other words, if an instruction dirties a page, can the very next instruction read the PTE and see the dirty bit set?

I don't care about the actual elapsed cycles, only if there is a software visible window in which the dirty bit is not yet set. I can't seem to find any guarantees in the reference manuals.

Answer 1

AMD64 Architecture Programmer’s Manual Volume 2: System Programming (revision 3.22, Sept. 2012)

In general, Dirty bit updates are ordered with respect to other loads and stores, although not necessarily with respect to accesses to WC memory; in particular, they may not cause WC buffers to be flushed. However, to ensure compatibility with future processors, a serializing operation should be inserted before reading the D bit.

(Emphasis mine.)

Answer 2

According to page 2033 of this document, Intel x86 caches information about the page table. The text states that if the dirty bit is cleaned by software, there's a possibility that the CPU still sees it as equal to 1.

Now, for the question: if the CPU caches the dirty bit, there's a possibility that the update to the PTE (page-table-entry) does not take place immediately. It could be delayed by a cache-write-back policy.

Page 1651 of the same document describes the WBINVD instruction, that flushes internal caches. It does not say that this includes all data cached by the CPU.