Confusion regarding Delay inside an always block in Verilog

Question

I am referring to the popular paper: Correct Methods For Adding Delays To Verilog Behavioral Models by Cummings

http://www.sunburst-design.com/papers/CummingsHDLCON1999_BehavioralDelays_Rev1_1.pdf

 always @(a or b or ci)
 #12 {co, sum} = a + b + ci;

From the paper,

a input changes at time 15 as shown in Figure 3, then if the a, b and ci inputs all change during the next 9ns, the outputs will be updated with the latest values of a, b and ci. This modeling style has just permitted the ci input to propagate a value to the sum and carry outputs after only 3ns instead of the required 12ns propagation delay.

Can anyone tell me why is this true? We are using a blocking assignment here. So,shouldn't the always block remain inactive from 15 to 27 ns because the current always block is not completed? But here it remains active , means always block gets triggered whenever a change is noticed.

Answer 1

It helps to reformat the code with a different layout to more accurately capture the functionality that is happening

always 
   @(a or b or ci)          // line 1
   #12                      // line 2
   {co, sum} = a + b + ci;  // line 3

The first line suspends the always process until it sees a change in one of the listed signals, which happens at time 15.

The second line suspends the process for 12 time units. During this time period, there are changes to a, b, and ci that are ignored.

The third line wakes up at time 27 (15+12) and uses the current values of a, b, and ci and makes a blocking assignment to {co, sum}.

Since this is a always block, after the assignment, it loops back to the first line and waits for another change.