Assign value to only one bit in a vector module output

Question

I have the following code and I get an error. I am trying to use only one bit out of the four lines in the inputs A, B, and the output, Y. To be clear, I do not want to use the AND operator, I want to use the AND module that I made.

AND_Gate_Quad_SN74AHCT08N and0(.A({3'bzzz,clk_disable}), .B({3'bzzz,clk}), .Y({3'bzzz,clk_buffer}));

What would be a good way to accomplish this?

Answer 1

An output port cannot be connected to numeric literal constant.

There at least three options I can think of

1. Do a simple connection and live with a port size mismatch warning .y(clk_buffer)
2. Declare as a 4-bit wire [3:0] clk_buffer and only use clk_buffer[0].
3. Create a 3-bit dummy_wire and use the connection .y({dummy_wire,clk_buffer}).