'Will an If statement stop checking if the first OR condition is met?

Does SystemVerilog evaluate the whole if statement or the minimum to get the result?

For example:

if (condition1 && condition2) begin
  ...
end

if (condition1 || condition2) begin
  ...
end

In the first case, will condition2 be evaluated if condition1 is False? In the second case, will condition2 be evaluated if condition1 is True?

if-statementsystem-verilog


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